SKEW ADJUSTMENT APPARATUS

摘要

First to N-th selection signals each instantaneously having a first logic level when representing selection and a second logic level when representing deselection are generated based on selection designation data. The first to N-th selection signals are individually latched, and first to N-th delayed selection signals are generated by individually delaying the first to N-th selection signals by a greater amount of delay when the latched selection signals transition from the first logic level to the second logic level than when the latched selection signals transition from the second logic level to the first logic level. A delayed data signal is selected corresponding to a delayed selection signal having the first logic level among the first to N-th delayed selection signals. The selected delayed data signal is output.

主权项

1. A skew adjustment apparatus for adjusting a skew of a clock signal based on an original data signal on which the clock signal is superimposed, the skew adjustment apparatus comprising:
a skew adjustment delay unit that generates first to N-th (N is an integer of 2 or more) delayed data signals being respectively delayed from said original data signal by N number of different amounts of delay; a decoder that generates first to N-th selection signals corresponding to the first to N-th delayed data signals and each instantaneously having a first logic level when it represents selection and a second logic level when it represents deselection, based on selection designation data applied thereto for designating selection of one of the first to N-th delayed data signals; first to N-th transition delay units that generate first to N-th delayed selection signals by individually latching and delaying the first to N-th selection signals; and a data selection unit that selects a delayed data signal corresponding to a delayed selection signal having the first logic level among the first to N-th delayed selection signals from among the first to N-th delayed data signals, and outputs the delayed data signal selected, wherein the first to N-th transition delay units delaying the first to N-th selection signals by a greater amount of delay when the respective selection signals transition from the first logic level to the second logic level according to the selection designation data than when the respective selection signals transition from the second logic level to the first logic level.