发明名称 Cache device and control method for controlling cache memories in a multiprocessor system
摘要 In the case that at the time of generation of a pre-fetch request following a read request from one of the processors the data stored in other cache devices cannot be read unless its state tag is changed, a cache controller carries out weak read operation for causing failure in the pre-fetch request as a fetch protocol. Alternatively, the cache controller reads pre-fetch data without changing state tags of other cache devices, sets a weak read state (W), and stores the data. The data in the weak read state (W) is invalided by synchronization operation of memory consistency by software. Furthermore, the pre-fetch data is stored in a passive preservation mode in the present cache device. Even if the pre-fetch data corresponds to a read request from some other cache device, the preservation of the data is not informed to the other cache device.
申请公布号 US6918009(B1) 申请公布日期 2005.07.12
申请号 US20010786049 申请日期 2001.06.18
申请人 FUJITSU LIMITED 发明人 SATO MITSURU;KUMON KOUICHI
分类号 G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/08
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