| 发明名称 |
SIGNAL GENERATING CIRCUIT USING FLIPPFLOP CIRCUIT |
| 摘要 |
PURPOSE:To make it possible to generate signals with hysteresis characteristics by obtaining the logical sums between outputs of two FFs, to which the input status is written by clock pulses, and between the input signal and the output of the post-stage FF and by inputting them to the pre-stage FF. |
| 申请公布号 |
JPS5399859(A) |
申请公布日期 |
1978.08.31 |
| 申请号 |
JP19770014864 |
申请日期 |
1977.02.12 |
| 申请人 |
NIPPON ELECTRIC CO;NIPPON ELECTRIC ENG |
发明人 |
KODAMA YUKIO;IGUCHI HIROSHI |
| 分类号 |
G04F5/00;G04G21/00;G04G99/00;H03K5/00;H03K5/1254;H03K5/15;H04L25/08 |
主分类号 |
G04F5/00 |
| 代理机构 |
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代理人 |
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| 地址 |
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