| 摘要 |
PURPOSE:To provide a semiconductor device wherein it enhances an integration intensity and it can be arranged efficiently. CONSTITUTION:A memory cell 24 and a memory cell 42 which are adjacent are formed as a two-layer structure by a first layer 1 and a second layer 2. Driver transistors 4a, 4b for the memory cell 24, access transistors 6a, 6b and driver transistors 4c, 4d for the memory cell 42 are formed in the first layer 1. Load transistors 5a, 5b for the memory cell 24, load transistors 5c, 5d for the memory cell 42 and access transistors 6c, 6d are formed in the second layer 2. The transistors formed in the first layer 1 are NMOS transistors, and the transistors formed in the second layer are PMOS transistors.
|
