Circuit for varying read timing

摘要

A circuit changes the timing for reading data by varying bias potential applied to a clock signal used to read the data. The circuit has a comparator for comparing an external clock signal with a reference voltage that provides a logic decision level and generating an internal clock signal, and a logic circuit for fetching input data in synchronization with the internal clock signal. The comparator has a bias changer. The bias changer applies DC bias potential to the external clock signal to the comparator, to change the phase of the internal clock signal.