发明名称 |
Depletion mode MOS capacitor with patterned Vt implants |
摘要 |
A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).
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申请公布号 |
US5986314(A) |
申请公布日期 |
1999.11.16 |
申请号 |
US19970947209 |
申请日期 |
1997.10.08 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SESHADRI, ANAND;STRONG, BOB |
分类号 |
H01L21/8242;H01L29/94;(IPC1-7):H01L29/36;H01L29/78 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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