Semiconductor memory device with high voltage generation circuit

摘要

A semiconductor memory device is provided which incorporates a voltage generation circuit capable of generating a high voltage even when a low power voltage is applied to the device. To control the gate voltage of each cell included in a memory cell array, a negative voltage generating circuit connected to a row decoder is included in a boosting circuit. In the case of using a single power of a low voltage, the negative voltage generating circuit generates a negative high voltage during, for example, data erasing. The gate of each P-channel MOS transistor for data transfer is supplied with a pulse signal with an amplitude based on a voltage VCCH which is higher than an external power voltage VCC and obtained by boosting the voltage VCC. As a result, a high voltage can be transferred and output efficiently even if the external power voltage is low.