APPARATUS AND METHOD FOR DETECTING PATTERN DISTORTION AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To detect pattern distortion on a finished pattern and perform higher precision pattern distortion error verification by comparing a polygonized finishing predicted pattern with an inspection reference pattern. SOLUTION: Vertex number reducing means 4 reduces the vertex number outputted from means 3 for turning a predicted pattern profile to a polygon of vertex number to one which can be treated by a common CAD software. A finishing predicted pattern data retaining part 5 retains polygon data with the vertex number thereof being reduced. Further, inspection reference pattern forming means 6 forms a reference pattern used for detecting pattern distortion not smaller than a permissible range from a design layout pattern data and an inspection reference pattern data retaining part 7 retains it. Pattern distortion detecting means 8 compares a finishing predicted pattern with a comparison reference pattern and extracts the part wherein pattern distortion not smaller than a permissible range occurs and a pattern distortion information retaining part 9 retains it.