发明名称 |
Use of Data Latches in Multi-Phase Programming of Non-Volatile Memories |
摘要 |
A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
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申请公布号 |
US2007097744(A1) |
申请公布日期 |
2007.05.03 |
申请号 |
US20060566583 |
申请日期 |
2006.12.04 |
申请人 |
LI YAN;CERNEA RAUL-ADRIAN |
发明人 |
LI YAN;CERNEA RAUL-ADRIAN |
分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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