| 摘要 |
An analog-to-digital converter (ADC) includes at least first thru third ADC slices configured to sample input signal and transmit first thru third digitally converted values thereof, at least one reference ADC slice configured to sample input signal and transmit a digitally converted reference value, first thru third and reference registers coupled to first thru third and reference ADC slices, respectively, a delay register having an input and output, and configured to produce a sample time adjustment signal, where the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the input signal by the second ADC slice, and a plurality of computational circuit elements coupled to the input, output, and the registers, and configured to determine values of an error, an approximate time derivative of the input signal estimated from the third, second and first sampled time point, and the sample time adjustment signal. |
| 主权项 |
1. An analog-to-digital converter (ADC) circuit comprising:
at least a first, a second, and a third ADC slice configured to sample an analog input signal and transmit a digitally converted signal thereof representative of a first, a second, and a third value of the analog input signal at a first, a second, and a third consecutively sampled time point thereof, respectively; at least one reference ADC slice configured to sample the analog input signal and transmit a digitally converted reference value to facilitate determining an error value; a first, a second, and a third register coupled to said first, second, and third ADC slices, and configured to store the first, second, and third values, respectively; a reference register coupled to said at least one reference ADC slice, and configured to store the reference value; a delay register comprising an input and an output, and configured to produce a sample time adjustment signal, wherein the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the analog input signal by said second ADC slice; and a plurality of computational circuit elements coupled to said input, said output, said first, second, and third registers, and said reference register, and configured to determine the error value, a value of an approximate time derivative of the analog input signal estimated from the third, the second, and the first sampled time point, and a value of the sample time adjustment signal. |
