Systems and methods for setting logic to a desired leakage state

摘要

Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

主权项

1. A circuit comprising:
combinational logic; and a plurality of sequential logic units configured to output values to the combinational logic, thereby affecting a state of the combinational logic; wherein a first subset of the sequential logic units is configured to reset to a single, first binary state, and wherein a second subset of the sequential logic units is configured to reset to a single, second binary state, the first and second binary states being different; and further wherein the plurality of sequential logic units are configured to collectively output a multi-bit binary value to the combinational logic when the sequential logic units are forced to reset, wherein the combinational logic is included in a pipeline stage of a processor.