发明名称 |
Non-Volatile Static RAM and Method of Operation Thereof |
摘要 |
A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored. |
申请公布号 |
US2016365145(A1) |
申请公布日期 |
2016.12.15 |
申请号 |
US201514864594 |
申请日期 |
2015.09.24 |
申请人 |
Cypress Semiconductor Corporation |
发明人 |
Ashokkumar Jayant;VERHAEGHE Donald J.;DeVilbiss Alan;Li Qidao;CHU Fan;Allen Judith |
分类号 |
G11C14/00;G11C11/419;G11C11/22 |
主分类号 |
G11C14/00 |
代理机构 |
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代理人 |
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主权项 |
1. A memory device, comprising:
a static random access memory (SRAM) circuit including a first data latch node and a second data latch node, the first data latch node configured to be maintained at a first voltage representing one bit of binary data and the second data latch node configured to be maintained at a second voltage representing one bit of complementary binary data; a non-volatile (NV) circuit including a first ferroelectric capacitor (F-Cap) coupled to the first data latch node and configured to store the one bit of binary data, wherein the first F-Cap is further coupled to a first bit-line and configured to output the one bit of binary data thereto; and a discharge circuit including first and second discharge transistors controllable by a common discharge signal, wherein a source terminal of the first discharge transistor is configured to be coupled to ground and a drain terminal of the first discharge transistor is coupled to the first F-Cap to provide a discharge path for charges accumulated thereat. |
地址 |
San Jose CA US |