| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a pulse delay circuit by a multiple phase clock system where a pulse can be delayed by a multiple phase clock signal which is asynchronous with an input clock signal and input pulse width can be stored. <P>SOLUTION: A rise edge of an input pulse signal 401, which is detected by a rise detecting means 404, is delayed by a rise pulse fixing delay circuit 408 by using quadrature clock signals 402-1,402-2,402-3,402-4 which are asynchronous with an input pulse signal 401, a fall edge of the input pulse signal 401, which is detected by a fall detecting means 405, is delayed by using quadrature clock signals 403-1, 403-2, 403-3 and 403-4 which are asynchronous with the input pulse signal 401, and a delayed pulse 413 is outputted by a pulse creation means 412 from an output pulse of the rise pulse fixing delay circuit 408 and an output pulse of the fall pulse fixing delay circuit 409. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
