DATA PROCESSOR AND MOBILE COMMUNICATION TERMINAL

摘要

PROBLEM TO BE SOLVED: To avoid the unexpected omission through carelessness of arithmetic results through an accelerator means by stopping the change of an internal clock signal that synchronizes specific arithmetic processing through a clock control circuit at the time of interrupting processing through an arithmetic processing means. SOLUTION: Arithmetic results of an output register 226 which are read by a processor core 120 are written to a program/data shared memory 112. When an interrupt is demanded to the core 120 in the process, an interrupt request is masked through an interrupt controller 121 about an interrupt that has a low priority and the occurrence of an interrupt is inhibited. In the case of an interrupt that has a high priority, the controller 121 supplies an interrupt signal INT to an accelerator 200. That stops the supply of a clock signal to the accelerator 200 without operating accelerator correspondence bits of a module stop register.