发明名称 Merged memory and logic (MML) integrated circuits including built-in test circuits and methods
摘要 MML integrated circuits include a memory block and a logic block that is connected to the memory block. A test enable pad and a test results pad are also provided. The MML integrated circuit also includes a built-in self-tester that is responsive to a test enable signal on the test enable pad, to test the memory block and to provide the test results on the test results pad. A clock pad may also be provided wherein the built-in self-tester is responsive to the test enable signal on the test enable pad and to a clock signal on the clock pad. The built-in self-tester preferably tests the memory block by providing control signals to the memory block and obtaining data that is read from the memory block.
申请公布号 US6158036(A) 申请公布日期 2000.12.05
申请号 US19980059754 申请日期 1998.04.14
申请人 SAMSUNG ELECTRONIC CO., LTD. 发明人 KWAK, JONG-TAEK
分类号 G11C29/18;(IPC1-7):G01R31/28;G11C29/00 主分类号 G11C29/18
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