| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the size and configuration of a circuit constituting a semiconductor memory. SOLUTION: A level shift circuit 13 is connected to a block selecting circuit 12 and a selection control circuit 16, and provided for each selection control circuit 16 respectively. A row selecting circuit 14 is connected to a block selecting circuit 12 and a selection control circuit 16, and provided commonly for a plurality of selection control circuit 16. The selection control circuit 16 is connected to a memory cell block 5, and provided for each memory cell block 5. The selection control circuit 16 activates selectively a specific memory cell transistor 1 in accordance with block selection information BS inputted from the level shift circuit 13 and line selecting signals LW1-LW8, LS1-LS4 inputted from a potential switching circuit 14.</p> |
