| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit in which layout of a defective address storing circuit is improved and increment of access time due to wiring delay is suppressed. SOLUTION: A memory cell array 10 is divided into an upper part cell array 10a and a lower part cell array 10b consisting of plural banks respectively. A column of row decoders 20 is arranged at a word line end part of the memory cell array 10 and a column decoder 30 is arranged at a bit line end part. The memory cell array 10 comprises a redundant cell array for replacing a defective cell by a normal cell array. A fuse circuit 40 which stores a defective address and controls replacement of a defective cell by coincidence detection with an address externally supplied is divided into two columns of fuse circuits 40a, 40b, fuse sets of each fuse circuit 40a, 40b are arranged in the direction of word line of the memory cell array 10, and the columns of fuse circuits 40a, 40b are arranged in the direction of bit line.</p> |
