| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device in which the area of a cell array can be reduced, regarding the non-volatile semiconductor storage device manufactured in a CMOS (complementary metal oxide semiconductor) process. <P>SOLUTION: In a memory cell 51, the substrate contact regions of NMOS (n-channel MOS) transistors 2 and the well contact regions of PMOS (p-channel MOS) transistors 1 are arranged in the vertical direction to floating gates 7. The cell array 50 is constituted so that the memory cells 51 and the memory cells arranging the memory cells 51 in a linear symmetry are disposed alternately in a row direction (X), and sub-arrays 51C are constituted and the sub-arrays disposed in the row direction (X) are arranged in parallel or arranged in the linear symmetry in the line direction (Y). Accordingly, since the substrate contact regions, the well contact regions and the diffusion regions of PMOS transistors can be used in common among the adjacent memory cells; the areas of the cell arrays can be reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
