FPGA ARCHITECTURE AT CONVENTIONAL AND SUBMICRON SCALES

摘要

Reconfigurable logic devices (500) and methods of programming the devices are disclosed. The logic device includes a look-up table (600, 600') (LUT) and at least one storage element (570) configured for sampling LUT output signals (520). The LUT (600, 600') comprises a plurality of input signals (510), an array of programmable impedance devices (110) operably coupled to the input signals (510), and the LUT output signals (520). Each programmable impedance devices (110) in the array includes a first electrode (120) operably coupled to one of the input signals (520), a second electrode (130) disposed to form a junction (150) wherein the second electrode (130) at least partially overlaps the first electrode (120), and a programmable material (140) disposed between the first electrode (120) and the second electrode (130). The programmable material (140) operably couples the first electrode (120) and second electrode (130) such that each programmable impedance device (110) exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional array (700, 700') or two-dimensional array (610, 610').