Sublithographic width finFET employing solid phase epitaxy

摘要

A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

主权项

1. A semiconductor structure comprising:
at least a field effect transistor, said field effect transistor comprising:
a portion of a single crystalline semiconductor material layer;a plurality of epitaxial semiconductor fins in epitaxial alignment with a crystalline structure of said portion of said single crystalline semiconductor material layer and having a uniform lateral thickness throughout;a stack of a gate dielectric and a gate electrode straddling over a center portion of each of said plurality of epitaxial semiconductor fins;a plurality of fin source regions located within a first end portion of each of said plurality of epitaxial semiconductor fins;a plurality of fin drain regions located within a second end portion of each of said plurality of epitaxial semiconductor fins;a planar source region located in a first surface portion of said single crystalline semiconductor material layer, wherein said planar source region is located beneath and vertically contacts each of said plurality of fin source regions; anda planar drain region located in a second surface region of said single crystalline semiconductor material layer, wherein said planar drain region is located beneath and vertically contacts each of said plurality of fin drain regions; and a shallow trench isolation structure embedded in an upper portion of said single crystalline semiconductor material layer, wherein a top surface of said shallow trench isolation structure is coplanar with a top surface of said planar source region and a top surface of said planar drain region.