| 摘要 |
Methods and apparatus are provided for using a partially functional memory device with extra fail bits to create a fully functional monolithic device. The concept may be expanded for use in waferscale integration. The concept may also be used to create a fully functional memory board using partially functional memory chips. To accomplish this, a distinct fail bit array is added to each memory chip and the defective bits in the main chip are replaced by bits in the fail bit array using a programmable element, such as a programmable logic array (PLA). The PLA generates fail bit access addresses to locations in the fail bit memory that replace the defective bits in the main array. Thus, the external address is simultaneously applied to both the main array and to the PLA. If there is a match between the external address and an internal location in the PLA, the PLA outputs a flag and a fail bit address which are used to disable the main array access and to enable access to the fail bit memory. |
