| 摘要 |
A pointer processor circuit substantially eliminates the pointer gap during justification of an outgoing SONET/SDH frame relative to an incoming SONET/SDH frame. The pointer interpreter circuit PI is constructed to receive an incoming frame, interpret the pointer H1H2, and write data payload bytes of the incoming frame into a FIFO memory. An input clock CLK1 controls the writing of data payload bytes into the FIFO. The FIFO stores only data bytes. A pointer generator circuit PG is coupled to the FIFO and is constructed to read out data payload bytes from the FIFO, create an outgoing frame, and calculate a new pointer. An output clock CLK2 controls reading of data from the FIFO to form an outgoing frame. The PI, FIFO and PG cooperate for justification of the outgoing frame relative to the incoming frame. The PG is constructed to determine the time X between justifications, to count justifications, and to determine the occurrence of N justifications corresponding to a row N data payload bytes of the SONET/SDH frame in the time (N-1)X adjacent to a pointer gap time interval (R+1)X of no justifications corresponding to R transport overhead bytes of the row. The PG is also constructed to average approximately and spread out the justifications over the interval X (N+R) by spacing the justifications to occur at intervals of approximately X (1+R/N), thereby substantially eliminating the pointer gap. Whole integer approximations are typically used for spacing the justifications during justification steps along a row of the SONET/SDH frame.
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