| 摘要 |
The invention relates to a layout structure of a semiconductor device and more particularly to a layout structure of column pass transistors in a semiconductor memory device where the area occupied with the transistors is reduced to the minimum allowable. Thus, in spite of high integration of the semiconductor memory device and miniaturization of memory cells, the column path transistors can be kept in an efficient arrangement. In the aforementioned layout structure, the active regions of the column path transistors are longitudinally in perpendicular to the bit line pairs, thereby making it possible to reduce the area occupied in terms of the total number of memory cells.
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