| 摘要 |
A synchronizing signal detecting circuit is disclosed. The sycnhronizing signal detecting circuit is characterized in that full matching or n mismatching is determined depending on a sub code area, a main data area, and the state of a system. Input data are compared with a predetermined synchronizing pattern and then a synchronizing signal is detected depending on the determined matching degree. As a result, since the synchronizing signal is detected, it is possible to minimize the missing synchronizing signal. The synchronizing signal detected in error is primarily removed using the window signal and the remaining synchronizing signal detected in error is finally removed by the error flag signal err_flag output as a result of ID ECC. Therefore, the actual synchronizing signal and the forcible synchronizing signal do not occur simultaneously, so that error detection of the synchronizing signal can be minimized. Furthermore, since the window area is varied depending on the state of the system, the sub code area, the main data area, each initial area of each area, and the other areas, it is possible to minimize the missing synchronizing signal. In addition, since the data are realigned and output in parallel, the accurate data can be output even if data slip occurs, thereby preventing error operation.
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