发明名称 |
Method and system for embedded chip erase verification |
摘要 |
A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.
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申请公布号 |
US6331951(B1) |
申请公布日期 |
2001.12.18 |
申请号 |
US20000717550 |
申请日期 |
2000.11.21 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
BAUTISTA, JR. EDWARD V.;HAMILTON DARLENE G.;LEE WENG FOOK;CHEN PAU-LING;WONG KEITH H. |
分类号 |
G11C16/02;G11C11/56;G11C16/04;G11C16/34;(IPC1-7):G11C16/06 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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