| 摘要 |
Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling module 105 is provided for each interrupt. An interrupt group setting register 154 holds a group number of an interrupt signal INT entered to the interrupt factor controlling module 105 . An interrupt group mask register 103 holds, for each group, information as to whether or not an interrupt belonging to a group in question is to be masked. In case an interrupt has occurred and the group of the group number of the interrupt, as held by the interrupt group setting register 154 , is specified by the interrupt group mask register 103 as being to be masked, the interrupt mask circuit 152 masks the interrupt.
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