Reduced dynamic power D flip-flop

摘要

A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial signaling technique. A clock inverter module may be used to provide a partial inverse clock signal that is the complement of a clock signal when a non-clock dependent input to the clock inverter module has a first value and to provide a fixed signal when the non-clock dependent signal has a second value. One or more MOSFETs controlled by the partial inverse clock signal do not charge or discharge when the non-clock dependent signal has the second value.

主权项

1. A D flip-flop having an input D and an output Q comprising a plurality of MOSFETs and a clock inverter module receiving a clck signal and a non-clock dependent signal as inputs and outputting a partial inverse clock signal, wherein at least one of the MOSFETs has a gate connected to the partial inverse clock signal and the clock inverter module is configured to output the partial inverse clock signal such that the partial inverse clock signal comprises a complement of the clock signal when the non-clock dependent signal has a first value and has a fixed value when the non-clock dependent signal has a second value, so that the at least one MOSFET having a control input connected to the partial inverse clock signal does not charge or discharge when the non-clock dependent signal has the second value, wherein the non-clock dependent signal is selected from the group consisting of the input D and an output signal of the D flip-flop.