发明名称 Semiconductor device and manufacturing method thereof
摘要 In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
申请公布号 US9515107(B2) 申请公布日期 2016.12.06
申请号 US201514986119 申请日期 2015.12.31
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kurokawa Yoshiyuki;Ikeda Takayuki;Tamura Hikaru;Kozuma Munehiro;Ikeda Masataka;Aoki Takeshi
分类号 H04N5/355;H01L27/146;H01L29/786;H01L31/105 主分类号 H04N5/355
代理机构 Robinson Intellectual Property Law Office, P.C. 代理人 Robinson Eric J.;Robinson Intellectual Property Law Office, P.C.
主权项 1. A semiconductor device comprising: a first pixel; and a second pixel, wherein the first pixel comprises: a first photoelectric conversion element;a first transistor; anda second transistor, wherein the second pixel comprises: a second photoelectric conversion element;a third transistor; anda fourth transistor, wherein the first transistor is configured to output a signal corresponding to a potential of a first signal charge accumulation portion, wherein the second transistor is configured to control charge accumulation in the first signal charge accumulation portion performed by the first photoelectric conversion element, wherein the third transistor is configured to output a signal corresponding to a potential of a second signal charge accumulation portion, wherein the fourth transistor is configured to control charge accumulation in the second signal charge accumulation portion performed by the second photoelectric conversion element, wherein a channel formation region in the second transistor comprises an oxide semiconductor, wherein a channel formation region in the fourth transistor comprises an oxide semiconductor, wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, wherein a reset operation in the first pixel and a reset operation in the second pixel are performed at substantially the same time, and wherein a timing of a read operation in the first pixel and a timing of a read operation in the second pixel are different from each other.
地址 Atsugi-shi, Kanagawa-ken JP