发明名称 MULTI-MEDIA INFORMATION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To easily make a pipeline without complicated system constitution and to reduce the time required at the time of inputting→processing→communicating continuous data packets as the whole. SOLUTION: Input buffer memory circuits 1121 and 1122 having two circuits for storing input data are prepared and two circuits output buffer memory circuits 1301 and 1302 for storing compressed data are prepared. Them, a processor 120 and transfer control circuits 111 and 131 perform pipeline processing for compression-processing multi-media information inputted to the other input buffer memory circuit parallelly to the input processing of the multi-media information to one of the input buffer memory circuits and transmission- processing the multi-media information transferred to the other output buffer memory circuit parallelly to the transfer processing of the compression-processed multi-media information to one of the output buffer memory circuits.
申请公布号 JPH11234132(A) 申请公布日期 1999.08.27
申请号 JP19980033434 申请日期 1998.02.17
申请人 MEIDENSHA CORP 发明人 TAKAI JUNICHI
分类号 H03M1/12;H03M7/30;H04L12/801;H04L12/861;H04L12/911;H04N21/433;H04N21/4402 主分类号 H03M1/12
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