发明名称 |
Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop |
摘要 |
The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.
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申请公布号 |
US2001043101(A1) |
申请公布日期 |
2001.11.22 |
申请号 |
US20010919926 |
申请日期 |
2001.08.02 |
申请人 |
OGAWA KATSUHISA;OHMI TADAHIRO;SHIBATA TADASHI |
发明人 |
OGAWA KATSUHISA;OHMI TADAHIRO;SHIBATA TADASHI |
分类号 |
H03H11/26;H03K3/03;H03K3/354;H03K5/00;H03K5/13;H03L7/081;H03L7/099;(IPC1-7):H03L7/06 |
主分类号 |
H03H11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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