| 摘要 |
The invention relates to an integrated circuit (1), especially an ASIC, comprised of a plurality of logic gates (2). A self-test circuit (3) is provided for conducting an internal self-test of the plurality of logic gates (2). Said self-test circuit comprises a test pattern generator (4) and a test response analyzer (5). In addition, an input/output circuit (7) which is provided in the integrated circuit enables a test of an external circuit (14, 15) to be conducted with the self-test circuit (3), said self-test circuit being integrated in the integrated circuit. |
