Insulated gate turn-off device with turn-off transistor

摘要

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.

主权项

1. An insulated gate turn-off (IGTO) device formed as a die comprising:
a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type overlying the first semiconductor layer; a third semiconductor layer of the first conductivity type overlying at least a portion of the second semiconductor layer; an array of cells comprising a plurality of insulated gate regions within trenches formed at least within the third semiconductor layer; at least some of the cells comprising:
a first semiconductor region of the second conductivity type overlying the third semiconductor layer and adjacent to an insulated gate region;a second semiconductor region of the first conductivity type overlying the first semiconductor region and adjacent to the insulated gate region;a third semiconductor region of the second conductivity type adjacent the first semiconductor region and the second semiconductor region and being more highly doped than the first semiconductor region; anda first conductor shorting the second semiconductor region to the third semiconductor region,wherein the first semiconductor region, the second semiconductor region, and the third semiconductor layer form a MOSFET, where a voltage applied to the insulated gate region greater than a threshold voltage of the MOSFET inverts the first semiconductor region adjacent to the insulated gate region to form a lower resistance path between the second semiconductor region and the third semiconductor layer to reduce a beta of a bipolar transistor formed by the third semiconductor region, the third semiconductor layer and the second semiconductor layer to turn off the IGTO device.