STI recess method to embed NVM memory in HKMG replacement gate technology

摘要

The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.

主权项

1. An integrated circuit (IC), comprising:
a semiconductor substrate having an upper substrate surface; a shallow trench isolation (STI) region made of a dielectric material disposed in the semiconductor substrate, wherein the STI region includes non-planar peripheral regions, which extend upward above the upper substrate surface, and also includes a central region, which is recessedly arranged between the non-planar peripheral regions; a conductive body which is arranged over the central region and which has a planar upper surface; and a contact which is ohmically coupled to the planar upper surface of the conductive body and which is arranged over the central region.