发明名称 Method for fabricating a trench capacitor of DRAM
摘要 A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF<SUB>2</SUB>. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.
申请公布号 US6979613(B1) 申请公布日期 2005.12.27
申请号 US20030707027 申请日期 2003.11.16
申请人 NANYA TECHNOLOGY CORP. 发明人 WU KUO-CHIEN;HSU PING
分类号 H01L21/20;H01L21/334;H01L21/8242;(IPC1-7):H01L21/824 主分类号 H01L21/20
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