PARALLEL DATA PROCESSING APPARATUS

摘要

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.

主权项

1. An array controller for controlling operation of a single instruction multiple data (SIMD) array of processing elements, comprising:
memory for maintaining results corresponding to instruction execution while executing load/store instructions and processing element instructions, the load/store instructions encoded with information indicating which registers of a register file of the respective processing elements are accessed by the respective load/store instructions; an instruction table to provide a first plurality of register indicators when addressed by a plurality of bits of a first processing element instruction to be executed; an instruction launcher, the instruction launcher to receive the first plurality of register indicators and to lock first respective registers of the register file that correspond to the first plurality of register indicators when the first processing element instruction is launched.