Multi-mode phase-frequency detector for clock and data recovery

摘要

A clock and data recovery (CDR) circuit produces an in-phase clock, a quadrature clock offset by 90 degrees from the in-phase clock, and an auxiliary clock offset from the in-phase clock by a fraction of 90 degrees. A data sampler cyclically samples a data signal to form sets of samples according to the in-phase, quadrature, and auxiliary clocks, each set comprising an in-phase sample, a quadrature sample, and an auxiliary sample. A CDR logic circuit processes the samples to form a timing word for each set.

主权项

1. A clock and data recovery (CDR) circuit comprising:
a phase interpolator configured to interpolate from various phases of a multi-phase clock to provide an in-phase clock, a quadrature clock offset in phase by a quadrature phase offset from the in-phase clock, and an auxiliary clock offset in phase from the in-phase clock by a fraction of the quadrature phase offset; a data sampler configured to sample a data signal to form a set of samples comprising an in-phase sample sampled responsive to the in-phase clock, a quadrature sample sampled responsive to the quadrature clock, and an auxiliary sample sampled responsive to the auxiliary clock; and a CDR logic circuit configured to process a first pair of samples from the set of samples and to process a second pair of samples from the set of samples to control the interpolation by the phase interpolator, wherein the second pair of samples is different from the first pair of samples.