| 发明名称 | Dual edge pulse de-multiplexer with equalized path delay | ||
| 摘要 | A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer. | ||
| 申请公布号 | US9484918(B1) | 申请公布日期 | 2016.11.01 |
| 申请号 | US201514834837 | 申请日期 | 2015.08.25 |
| 申请人 | HRL Laboratories, LLC | 发明人 | Kuan Yen-Cheng;Ku Ining;Xu Zhiwei A.;Morton Susan L.;Hitko Donald A.;Petre Peter;Cruz-Albrecht Jose;Reamon Alan E. |
| 分类号 | H03K19/003;H03K19/00 | 主分类号 | H03K19/003 |
| 代理机构 | Ladas & Parry | 代理人 | Ladas & Parry |
| 主权项 | 1. A pulse domain 1 to 2N demultiplexer comprising: i. a pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of said counters being responsive to leading edges of the pulses in said incoming pulse train and the other one of said counters being responsive to trailing edges of the pulses in said incoming pulse train; ii. control logic responsive to the states through which said pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of said pulse domain 1 to 2N demultiplexer. | ||
| 地址 | Malibu CA US | ||