Method and apparatus for word-level netlist reduction and verification using same

摘要

A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.

主权项

1. A method for processing a computer implemented representation of a circuit design, comprising:
representing the circuit design in memory accessible by a computer as a data structure defining a netlist as a plurality of nodes, and identifying a first set of nodes that includes word-level datapath nodes for corresponding words; using the computer, segmenting word-level datapath nodes in the first set of nodes in the data structure into segmented nodes having segment widths corresponding to uniformly treated segments of the corresponding words; using the computer, finding reduced safe sizes for the segmented nodes; and using the computer, generating an updated data structure representing the same circuit design, using the reduced safe sizes of the segmented nodes, wherein the reduced safe sizes of at least some of the segmented nodes are more than one bit.