Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC

摘要

This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.

主权项

1. A data processing system comprising:
a plurality of processing cores, at least one processing core including cache memory for temporarily storing data; a plurality of memory endpoints storing data; a plurality of access arbitrators, one corresponding to each of said plurality of memory endpoints, each access arbitrator granting access to said corresponding memory endpoint to only single requesting processing core based upon a priority level, a fair share count and a starvation count corresponding to each processing core; and a plurality of coherence units, one corresponding to each of said plurality of memory endpoints, each coherence unit including
a coherence maintenance address queue having a plurality of entries, each entry storing an address of an access request committed to the shared memory and an assigned ID tag,an ID allocation block coupled to said coherence maintenance address queue assigning an available ID tag from a set of ID tags to an access committed to the shared memory for storage in said coherence maintenance address queue and retiring a coherence maintenance address queue entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding access, anda comparator coupled to said input ports and said coherence maintenance address queue and receiving an address of a memory access request, said comparator comparing the address of the memory access request with all addresses stored in said coherence maintenance address queue and generating a hazard stall signal if the address of the memory access request matches any address stored in said coherence maintenance address queue.