System and method for increased capacity and scalability of a memory topology

摘要

A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface.

主权项

1. A memory expansion module for providing increased capacity and scalability of a memory topology, comprising:
a memory controller coupled to one or more processors; a channel buffer coupled to the memory controller, wherein the channel buffer receives control information from the memory controller, wherein the channel buffer resynchronizes one or more signals with a clock, and wherein the channel buffer amplifies at least one of the one or more signals; a plurality of memory modules coupled to the channel buffer by a plurality of point-to-point control distribution paths and by a plurality of point-to-point data paths, wherein the channel buffer transmits two or more copies of replicated control information to two or more of the plurality of memory modules; a plurality of differential read lines coupled to the channel buffer, wherein the plurality of differential read lines couple the channel buffer to the memory controller, and wherein the plurality of differential read lines are transceived via a first gated copy line of the plurality of point-to-point data paths; a plurality of differential write lines coupled to the channel buffer, wherein the plurality of differential write lines couple the channel buffer to the memory controller, and wherein the plurality of differential write lines are transceived via a second gated copy line of the plurality of point-to-point data paths; a plurality of differential command lines coupled to channel buffer, wherein the plurality of differential command lines couple the channel buffer to the memory controller, and wherein the plurality of differential command lines are transceived via a third gated copy line of the plurality of point-to-point control distribution paths; and wherein the plurality of differential read lines, the plurality of differential write lines, and the plurality differential command lines carry packets of information, and wherein the packets of information comprise a command packet, and wherein the command packet corresponds to a read packet or a write packet.