发明名称 Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering
摘要 A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.
申请公布号 US9495290(B2) 申请公布日期 2016.11.15
申请号 US200812144987 申请日期 2008.06.24
申请人 Sonics, Inc. 发明人 Wingard Drew E.;Chou Chien-Chun;Hamilton Stephen W.;Swarbrick Ian Andrew;Vakilotojar Vida
分类号 G06F9/46;G06F9/455;G06F12/06;G06F15/173 主分类号 G06F9/46
代理机构 Rutan & Tucker, LLP 代理人 Rutan & Tucker, LLP
主权项 1. An interconnect, the interconnect configured to allow for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect, wherein the interconnect implements logic distributed over the interconnect and configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions, wherein the logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction completes, where the logic does not include any reorder buffering, and while ensuring the expected execution order within the first transaction and second transaction are maintained.
地址 Milpitas CA US