Instruction and logic for processing text strings

摘要

Method, apparatus, and program means for performing a string comparison operation. An apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

主权项

1. A system on a chip comprising:
a graphics controller; a memory controller; and a processor, the processor comprising:
a first logic to fetch a compare instruction;a decoder logic to decode the compare instruction;a plurality of 64-bit single-instruction multiple data (SIMD) integer data registers, including:
a first and second 64-bit SIMD integer data register to store a first and second 64-bit SIMD integer operand, respectively, each of the first and second 64-bit SIMD integer operands to include a plurality of integer data elements; anda 64-bit SIMD destination register, into which at least one result of performing the compare instruction is to be stored, wherein the first and second 64-bit integer data registers and the 64-bit SIMD destination register are to be identified by a first and second SIMD operand field and a SIMD destination field, respectively, within the compare instruction, and wherein the instruction includes a field to indicate one of a plurality of data element sizes for data elements of the first and second 64-bit integer data operands, including an 8-bit data element size, a 16-bit data element size, and a 32-bit data element size; anda plurality of execution units, wherein at least one execution unit of the plurality of execution units is to execute the compare instruction, wherein the compare instruction is to cause the processor to:
compare integer data elements of the first 64-bit SIMD integer operand with integer data elements of the second 64-bit SIMD integer operand, wherein the integer data elements of the first 64-bit SIMD integer operand to be compared with the integer data elements of the second 64-bit SIMD integer operand are in the same data element position, andstore a plurality of indicators of whether the compared integer data elements of the first 64-bit SIMD integer operand and the integer data elements of the second 64-bit SIMD integer operand are equal,wherein the plurality of indicators are expanded data elements, each of a first multi-bit size.