Computer processor employing cache memory with per-byte valid bits

摘要

A computer processing system with a hierarchical memory system that associates a number of valid bits for each cache line of the hierarchical memory system. The valid bits are provided for each cache line stored in a respective cache and make explicit which bytes are semantically defined and which are not for the associated given cache line. Memory requests to the cache(s) of the hierarchical memory system can include an address specifying a requested cache line as well as a mask that includes a number of bits each corresponding to a different byte of the requested cache line. The values of the bits of the byte mask indicate which bytes of the requested cache line are to be returned from the hierarchical memory system. The memory request is processed by the top level cache of the hierarchical memory system, looking for one or more valid bytes of the requested cache line corresponding to the target address of the memory request. The valid bytes of the cache line corresponding to the byte mask as stored in cache can be identified by reading out the valid bit(s) and data byte(s) stored by the cache for putative matching cache lines for those data bytes that are specified by the byte mask of the memory request, while ignoring the valid bit(s) and data byte(s) stored by the cache for putative matching cache lines for those data bytes that are not specified by the byte mask of the memory request. Extensions to shared multiprocessor systems is also described and claimed.

主权项

1. A computer processing system comprising:
a hierarchical memory system having at least one cache; and a processor having execution logic that generates load memory requests that are supplied to the hierarchical memory system; wherein the at least one cache stores a plurality of cache lines as well as a plurality of valid bits for each cache line, wherein each cache line includes a plurality of data bytes, and wherein the plurality of valid bits for a given cache line correspond to the plurality of data bytes of the given cache line and provide an indication of the validity of the corresponding data bytes of the given cache line; wherein each given load memory request includes a cache line address that specifies a particular cache line as well as a request byte data that specifies at least one particular data byte of the cache line specified by the cache line address, and the cache is configured to process the given load memory request by i) accessing at least one cache line stored by the cache that putatively matches the cache line address of the load memory request, and ii) processing the valid bits of the accessed cache line together with the request byte data in order to output from the cache for supply to the execution logic only valid data bytes of the accessed cache line for those data bytes specified by the request byte data of the memory request.