Semiconductor memory device with plural memory die and controller die

摘要

A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.

主权项

1. A system comprising:
a memory controller configured to supply a global clock signal and an external read command via an external control bus; and a memory device separate from the memory controller and comprising a plurality of memory dies and a controller die, the memory device being communicatively coupled to the external control bus to receive the global clock signal and the external read command, and the controller die being configured to provide an internal read command to a selected one of the memory dies in response to the external read command and provide an internal clock signal synchronized with the global clock signal; wherein the selected memory die is configured to provide read data to the controller die in response to the internal read command, wherein a first latency from when the internal read command is sent by the controller die and the read data is received by the controller die differs for at least two of the memory dies, the first latency differing depending on which of the at least two memory dies is selected as the selected memory die; wherein the controller die is further configured to output the read data on an external data bus, wherein a second latency from when the controller die receives the external read command to when the controller die outputs the read data on the external data bus is uniform for the at least two memory dies when selected as the selected memory die; wherein the memory controller is communicatively coupled to the controller die via the external data bus.