| 主权项 |
1. A processor comprising:
an instruction fetch unit to fetch a plurality of instructions for a plurality of applications executing in a multitasking environment; an execution unit to execute the plurality of instruction; and a memory protection unit (MPU) to enforce memory access control for the plurality of applications, wherein the MPU comprises a memory protection table, wherein the memory protection table defines a plurality of code regions of the code memory and a plurality of data regions of the data memory, wherein the memory protection table links the plurality of code regions to the plurality of data regions, and wherein the memory protection table identifies access permissions for each of the plurality of code regions and the plurality of data regions, wherein the memory protection table identifies a specific privilege level for each of the plurality of code regions and the plurality of data regions, wherein the MPU is to:
define an instruction region (I-space) in an I-space register and a data region (D-space) in a D-space register;link the I-space to the D-space;receive an instruction address for a first instruction of the plurality of instructions from the instruction fetch unit and a data address of a data access operation for the first instruction from the execution unit;determine whether the instruction address and data address are within the I-space defined by the I-space register and within the D-space defined the D-space register; andissue a memory protection fault for the data access operation when the instruction address and data address are not within the I-space and D-space. |
