Flash memory controller with calibrated data communication

摘要

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

主权项

1. A flash memory controller, comprising:
a bus interface to couple to a plurality of flash memory devices, the bus interface including a circuit to send at least one signal to individually address a selected flash memory device of the plurality of flash memory devices and store a device-specific value in a reference voltage register of the selected flash memory device; and a transmitter to output a data signal to the selected flash memory device wherein the device-specific value stored in the reference voltage register of the selected flash memory device controls a reference voltage used by a corresponding receiver circuit of the selected flash memory device, the receiver circuit to receive the data signal transmitted by the flash memory controller to the selected flash memory device.