发明名称 Semiconductor integrated circuit with bist circuit
摘要 According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal. When the memory is tested using a BIST circuit, the first selection unit selects a memory signal output from the memory in response to the test signal. When the BIST circuit is tested, the first selection unit selects the bypass signal. If the memory is tested, the compression unit holds a signal output from the first selection unit and if the BIST circuit is tested, the compression unit compresses and holds the signal output from the first selection unit. The comparison unit compares the signal held in the compression unit with an expectation value signal of the memory signal which is generated in the BIST circuit.
申请公布号 US9443611(B2) 申请公布日期 2016.09.13
申请号 US201313942095 申请日期 2013.07.15
申请人 Kabushiki Kaisha Toshiba 发明人 Tokunaga Chikako;Anzou Kenichi
分类号 G11C29/00;G11C29/12;G11C29/02;G11C29/18;G11C29/40;G11C29/44;G11C29/04;G11C29/36 主分类号 G11C29/00
代理机构 White & Case LLP 代理人 White & Case LLP
主权项 1. A semiconductor integrated circuit, comprising: a memory configured to receive a test signal, which is used for a test of the memory, generated in a BIST (built-in self test) circuit; a bypass circuit configured to bypass the test signal to output a bypass signal; a first selection unit configured to select a memory signal output from the memory in response to the test signal when the memory is tested using the BIST circuit, the first selection unit being configured to select the bypass signal when the BIST circuit is tested; a compression unit configured to hold a signal output from the first selection unit when the memory is tested, the compression unit being configured to compress and hold the signal output from the first selection unit when the BIST circuit is tested; and a comparison unit configured to compare a signal held in the compression unit with an expectation value signal of the memory signal generated in the BIST circuit.
地址 Tokyo JP