Apparatuses and methods for generating a suppressed address trace

摘要

Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

主权项

1. A processor comprising:
a hardware execution unit to execute instructions; a hardware retirement unit to retire executed instructions; and a trace generator having a trace suppressor to output a suppressed address trace of the executed instructions, wherein a first executed instruction accessed a relative address referencing an address register, and the suppressed address trace comprises a register hint packet outputted for the first executed instruction.