发明名称 Atomic transactions to non-volatile memory
摘要 Durable atomic transactions for non-volatile media are described. A processor includes an interface to a non-volatile storage medium and a functional unit to perform instructions associated with an atomic transaction. The instructions are to update data at a set of addresses in the non-volatile storage medium atomically. The functional unit is operable to perform a first instruction to create the atomic transaction that declares a size of the data to be updated atomically. The functional unit is also operable to perform a second instruction to start execution of the atomic transaction. The functional unit is further operable to perform a third instruction to commit the atomic transaction to the set of addresses in the non-volatile storage medium, wherein the updated data is not visible to other functional units of the processing device until the atomic transaction is complete.
申请公布号 US9524219(B2) 申请公布日期 2016.12.20
申请号 US201314040380 申请日期 2013.09.27
申请人 Intel Corporation 发明人 Bahnsen Robert;Sakthivelu Sridharan;Saletore Vikram A.;Viswanathan Krishnaswamy;Tolentino Matthew E.;Govindaraju Kanivenahalli;Zimmer Vincent J.
分类号 G06F12/14;G06F11/14;G06F9/46 主分类号 G06F12/14
代理机构 Lowenstein Sandler LLP 代理人 Lowenstein Sandler LLP
主权项 1. A processing device comprising: a cache; an interface to a non-volatile storage medium (NVM) operatively coupled to the cache; and a first functional unit to execute a plurality of instructions associated with an atomic transaction and to track execution of the atomic transaction with a first transaction identifier (TID), wherein the plurality of instructions are to replace data at a set of addresses in the NVM atomically with new data, wherein the first functional unit is to execute the plurality of instructions to: perform a first instruction to create the atomic transaction that delineates a size of the data to be replaced atomically and generates the first TID;perform a second instruction to execute the atomic transaction including storing, in first cache lines of the cache, the new data with the set of addresses and the first TID;perform a third instruction to commit the atomic transaction to the set of addresses in the NVM, wherein the new data is not visible to other functional units until the atomic transaction is complete; andwherein the second instruction and the third instruction are further to, in response to a read request from a second functional unit to an address of the set of addresses: determine that the read request lacks the first TID;access the data associated with the address in a second cache line of the cache that is not associated with a valid TID in response to determining that the read request lacks the first TID, wherein the new data is simultaneously available in the first cache lines when accessing the data in the second cache line; andsend, to the second functional unit, the data for the address.
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