| 摘要 |
PURPOSE:To prevent an address transition detector output pulse period from being finished earlier than a decoder selecting period, by taking an output of an address buffer circuit as an input to an address transition detector circuit. CONSTITUTION:An output of the address buffer circuit from inverters INV3, INV6, not from nodes a1, a2 of the address buffer circuit generating a cell designating output of inverse logic being inputs to a decoder circuit selecting a storage cell, is impressed to an ATD circuit detecting the change in the designated output and outputting the address transition detector (ATD) pulse phiA. Thus, the pulse period of the pulse phiA is not finished earlier than the decoder selecting period, allowing to prevent the generation of malfunction due to the shift in the relation of relative time. |
